The rod drives the buzzer LS2 in Q1. Additionally, two buttons are connected to PORTA.3 and PORTA.2 respectively. One is a PWM button, which is used to control the PWM output port to drive the buzzer; the other is a PORT button, used to control the I/O port to drive the buzzer. The I/O port connected to the buttons has an internal pull-up resistor enabled.

Software Design Methods

Let's analyze the buzzer. The buzzer operates at a frequency of 2000Hz, meaning the waveform cycle of the driving signal is 500μs. Since it's a 1/2 duty signal, both the high and low level durations within a cycle are 250μs. In terms of software design, we will explain based on two driving methods.

PWM Output Directly Drives Buzzer

Since PWM controls the buzzer at a fixed frequency, the output waveform of PWM can be set during the system initialization of the program.

Firstly, based on the 10-bit data width of the PWM output cycle of SH69P43, the PWM clock is selected. The system uses a 4MHz crystal oscillator as the main oscillator, with each tosc taking 0.25μs. If the PWM clock is set to tosc, the buzzer's required waveform cycle of 500μs translates to a count of 500μs / 0.25μs = (2000)10 = (7D0)16. 7D0H is an 11-bit data, and the SH69P43's PWM

The output cycle width is only 10 bits, so selecting the PWM clock as tosc cannot achieve the drive waveform required by the buzzer.

Here, we set the PWM clock to 4tosc, making the PWM clock cycle 1μs. Therefore, the count value for 500μs is 500μs / 1μs = (500)10 = (1F4)16. This means that to set the output period, you fill in 1, F, and 4 in the high 2 bits, middle 4 bits, and low 4 bits of the period register, respectively. Next, we set the duty cycle register. The implementation of the duty cycle in PWM output is

The width of the level within a cycle is set. When the output mode is selected as normal, the duty cycle register is used to set the width of the high level. A width count of 250μs translates to 250μs / 1μs = (250)10 = (0FA)16. Simply fill in 0, F, and A in the high 2 bits, middle 4 bits, and low 4 bits of the duty cycle register, respectively, to set the duty cycle to 1/2 duty.

In the future, simply activate the PWM output, and the PWM output port will naturally produce a square wave with a frequency of 2000Hz and a duty cycle of 1/2 duty.

2. Timing flip-level drive for I/O port buzzer

The setup for driving a buzzer using the I/O port level flip timing method is quite simple; it only requires waveform analysis. Since the driving signal is a square wave with a period of 500μs and a duty cycle of 1/2 duty, a level flip is needed every 250μs to obtain the square wave signal for the buzzer driver. In the program, TIMER0 can be used for timing. Set the prescaler of TIMER0 to /1 and choose TIMER0's clock source as the system clock (main oscillator clock/4). By writing 00H to the high 4 bits and 06H to the low 4 bits of TIMER0's load/count register, the TIMER0 interrupt can be set to 250μs. When the buzzer needs to sound, simply flip the I/O port level once upon entering the TIMER0 interrupt. Set the I/O port level to low when the buzzer no longer needs to sound. Setting the I/O port output level to low when not sounding is to prevent leakage.